1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which generates an internal power voltage having a voltage level lower than the external power voltage, and uses the internal power voltage as a power voltage for the internal circuit.
2. Description of the Related Art
In the field of semiconductor memories such as the dynamic random access memory (DRAM) and the like, the miniaturization of semiconductor devices has recently progressed. As one part of the miniaturization process for the semiconductor devices, there is a technique for thinning the gate oxide film. However, as the thickness of the gate oxide film is reduced, the electrical field applied on the gate oxide film is naturally increased during the operation of the device, resulting in deterioration of the gate oxide film. The deterioration of the gate oxide film can be prevented without changing the voltage level of the external power voltage by reducing the electrical field applied to the gate oxide film during the operation. Therefore, there has been proposed a method of generating an internal power voltage which is lower than the external power voltage, by use of an on-chip voltage dropping circuit for dropping the external power voltage. With such a voltage dropping circuit, the internal circuit can be operated at a low internal power voltage even if an external power voltage having the same voltage level is to be applied to the semiconductor integrated circuit on which no voltage dropping circuit is provided. Therefore, the electrical field applied to the gate oxide film of an internal transistor can be reduced, thereby preventing the deterioration of the gate oxide film.
A known example of the semiconductor integrated circuit having a built-in voltage dropping circuit is disclosed in U.S. Pat. No. 4,585,955 (Yukimasa UCHIDA). This semiconductor integrated circuit includes a voltage dropping circuit for generating an internal power voltage having a low voltage level by dropping an external power voltage, a voltage comparison circuit and the like. The voltage dropping circuit consists of, for example, a P-channel MOS transistor, and serves to drop the external power voltage V.sub.CC supplied to a power terminal, and generate an internal power voltage V.sub.DD having a potential level lower than the V.sub.CC. The voltage comparison circuit compares the internal power voltage V.sub.DD with the reference voltage to detect V.sub.DD. The gate of the p-channel MOS transistor which constitutes the voltage dropping circuit is controlled by the detection output from the dropping circuit.
In the structure described above, when the voltage level of the internal power voltage V.sub.DD is decreased, an ON-stage resistance of the MOS transistor is reduced so as to compensate for the decrease in the voltage level. In contrast, when the voltage level of the V.sub.DD is increased, the MOS transistor is regulated so that the ON-stage resistance thereof is lowered to compensate for the increase in the voltage level. With the above-described operation, the internal power voltage V.sub.DD can be maintained at a constant voltage level.
The internal power voltage thus regulated to have a constant level is supplied as power voltage to the internal circuit, for example, made of a memory circuit and the like.
It is generally known that a semiconductor integrated circuit including a voltage dropping circuit has a narrow operation margin in the region where the level of the external power voltage is low. This is because a decrease in level of the internal power voltage within the low power voltage region has a great influence on the operation of the internal circuit, as compared to a decrease of voltage level which takes place in the region other than the low power voltage region.
Moreover, when the inner circuit is in the active state, that is, for example, when the internal circuit is of a DRAM type and the signal potential of a word line need to be boosted, or when the bit line is charged or discharged; a sudden and remarkable decrease in voltage level of the internal power voltage is exhibited. The decrease in level of the internal power voltage naturally reduces the operation margin of the internal circuit.
The main factor which causes the above-described drawbacks is that the detection output potential of the voltage comparison circuit cannot be set at the ground potential, which is completely 0V, though the detection output potential of the voltage comparison circuit can be lowered to a certain extent; therefore, the P-channel MOS transistor of the voltage dropping circuit is not rendered fully conductive, and the performance of the transistor cannot be demonstrated to a full extent. Such a decrease in voltage level of the internal power voltage cannot be followed sufficiently by the voltage dropping circuit, thereby interfering with the operation of the internal circuit.